1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to methods for sizing layout design geometries of transistor gates to achieve specific optimized performance characteristics.
2. Description of the Related Art
In the design of semiconductor integrated circuits, circuit designers commonly utilize what are known as xe2x80x9cstandard cellsxe2x80x9d to achieve a particular circuit response. Standard cells are essentially pre-designed layouts of transistors that are wired to perform a certain type of logical function. By way of example, a company, such as Artisan Components, Inc. of Sunnyvale, Calif., designs standard cell libraries incorporating many different types of standard cells, each for performing a specific type of logical operation or operations. The standard cells of the standard cell library are then used by integrated circuit design engineers in conjunction with modeling software to produce a larger scale circuit design that meets a particular specification.
A popular and most commonly used modeling software is a hardware description language (HDL) named xe2x80x9cVerilogxe2x80x9d (IEEE Verilog Standard 1364, 1995). Using Verilog, designers are able to describe each component of an integrated circuit in terms of its functional behavior as well as its implementation. Once a circuit design using Verilog is complete, the Verilog code is synthesized to generate what is referred to as a xe2x80x9cnetlist.xe2x80x9d A netlist is essentially a list of xe2x80x9cnets,xe2x80x9d which specify components (i.e., standard cells) and their interconnections which are designed to meet the circuit design""s performance constraints.
The actual placement plan of the standard cells on silicon and the topography of wiring is reserved for a subsequent xe2x80x9clayoutxe2x80x9d stage. In the layout stage, software tool, commonly referred to as xe2x80x9cplace and routexe2x80x9d software, is used to design the actual wiring that will ultimately interconnect the standard cells together. To do this, each standard cell typically has one or more pins for interconnection with pins of other standard cells. The netlist therefore defines the connectivity between pins of the various standard cells of an integrated circuit device.
Although the design of integrated circuits using specialized software has greatly simplified the design process, the ultimate design is only going to perform as well as the individual standard cells. That is, if standard cells are not individually optimized to meet a specific performance characteristic, the designer of the larger integrated circuit design will find it difficult, and many times, impossible to optimize the resulting larger design to meet some pre-set operation or performance characteristic.
To facilitate discussion, FIG. 1 shows a prior art standard cell 100 having a p-type transistor and an n-type transistor. The standard cell 100 has a cell height (Hcell) and a cell length (Lcell). Although standard cells that represent true logical circuits may implement additional transistors and have associated interconnection wiring (not shown) defined, this simplistic transistor level illustration shows how the standard cell 100 is divided in two parts. As is general practice in CMOS design, one part of the standard cell 100 is for p-type transistors 102 and the other part is for n-type transistors 104. In some situations, standard cell designers designed the gate width xe2x80x9cWpxe2x80x9d of the p-type transistor 102 to be equal to the gate width xe2x80x9cWnxe2x80x9d of the n-type transistor 104. A problem with this design is that p-type transistors are generally know to be weaker in driving strength than their n-type transistor counterparts. As a result, when a standard cell is designed having N and P type transistors with equal gate widths, the designer will need more chip space to design additional p-type transistors to meet the desired drive characteristics.
To combat this known problem, designers shifted their efforts in order come up with standard cells, in which, the drive strength of the p-type transistors substantially equaled the drive strength of the n-type transistors. To achieve this xe2x80x9cbalancedxe2x80x9d drive standard cell design, designers increased the size of the p-type transistors such that they were about 2 to 3 times larger in width that the stronger driving n-type transistors (i.e., ratio={Wp/Wn}=2xcx9c3). Thus, the simplistic design of FIG. 1 shows a case in which the p-type transistor has a gate width Wp that is about 2 or 3 times larger than the gate width Wn of the n-type transistor, thus achieving the desired balanced drive.
An undesirable impact of having P and N type transistors of standard cells with balanced drive is, however, that the standard cell is not optimized with transistor speed nor power consumption in mind. As a result, most balanced drive standard cell designs present substantial difficulties (e.g., due to a fixed standard cell delay) to circuit designers that must meet very tight specifications that require minimum delays in order to implement a fast integrated circuit design. Similarly, designers that face particular constraints to reduce power consumption are also currently required to assume a fixed power consumption specification for the particular standard cell and must, if possible, perform other possibly more expensive design modifications to control power consumption.
In view of the foregoing, there is a need for methods for designing standard cell designs that enable precise optimization of transistor delay characteristics. There is also a need for methods for designing standard cell designs that enable precise optimization of transistor power consumption characteristics.
Broadly speaking, the present invention fills these needs by providing methods for designing standard cell transistors to obtain optimum results in terms of reduced gate delay and power consumption characteristics. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a computer readable media, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, a method for designing standard cell transistor layouts is disclosed. The method includes defining a transistor model for a P-type transistor and an N-type transistor of a CMOS standard cell. The method then includes optimizing a ratio between the P-type transistor and the N-type transistor. The ratio is defined by dividing a P-type gate width of the P-type transistor by an N-type gate width of the N-type transistor. The optimizing is performed by substantially minimizing an average delay for the transistor structure. In this embodiment, the CMOS standard cell will define a transistor structure that is implemented to make a logic circuit. The CMOS standard cell is one of a library of standard cells, where each standard cell defines a particular logic circuit.
In yet another embodiment, a method for sizing transistors of a standard cell is disclosed. The method includes defining a transistor structure for the standard cell. The transistor structure defines a logic circuit upon being interconnected using interconnect metallization and conductive vias structures. The method then includes defining a transistor model for a P-type transistor and an N-type transistor of the standard cell. The P-type transistor is oriented on a first side of the standard cell and the N-type transistor is oriented on a second side of the standard cell. The method further includes generating a plurality of ratios between the P-type transistor and the N-type transistor, such that each of the plurality of ratios are derived by dividing a P-type gate width of the P-type transistor by an N-type gate width of the N-type transistor. The method then generates a plurality of average delays for the transistor structure of the standard cell. In this embodiment, each of the generated plurality of average delays is associated with a corresponding one of the plurality of ratios. The method then proceeds to identify an optimum ratio from the plurality of ratios by finding a low one of the plurality of average delays. In this embodiment, the low one the plurality of average delays is used to size the P-type gate width of the P-type transistor and the N-type gate width of the N-type transistor to obtain the most optimum reduced delay for a given standard cell design.
In still another embodiment, a method for sizing transistors of a standard cell for reduced power consumption is disclosed. The method includes defining a transistor structure for the standard cell. The transistor structure defines a logic circuit upon being interconnected using interconnect metallization and conductive vias structures. The method also includes defining a transistor model for a P-type transistor and an N-type transistor of the standard cell. The P-type transistor is oriented on a first side of the standard cell and the N-type transistor is oriented on a second side of the standard cell. Then, the method includes generating a plurality of ratios between the P-type transistor and the N-type transistor, such that each of the plurality of ratios is derived by dividing a P-type gate width of the P-type transistor by an N-type gate width of the N-type transistor. The method then includes generating a plurality of power consumption data for the transistor structure of the standard cell, such that each of the generated plurality of power consumption data is associated with corresponding ones of the plurality of ratios. The method now proceeds to identify an optimum ratio from the plurality of ratios by finding a low one of the plurality of power consumption data. The P-type gate width of the P-type transistor and the N-type gate width of the N-type transistor are now sized using the identified optimum ratio.
Advantageously, the various embodiments of the present invention provide methods for optimizing standard cell transistor layout design to produce logic circuits that have reduced capacitive loading delays. Accordingly, it is now possible to design faster standard cell circuitry on the same amount of chip space, without having to unnecessarily increase the number of transistors to achieve a desired faster speed. It is also important to take note that once the optimum ratio or range of ratios are found, the obtained ratios can be applied to any size standard cell, with the same functionality, and achieve substantially the same delay reducing benefits. In addition, because less transistors are needed in standard cells to achieve the optimum reduced delay, the layout of an integrated circuit can be made substantially more dense, thereby saving valuable chip space.
Furthermore, because the transistor layout is made more dense, the interconnect routing will be relaxed because there will be more open chip space over which to route the metallization interconnect lines. In another embodiment, the ratio optimization techniques are applicable for designing transistor devices to produce the least power consuming integrated circuit device. Not only do the embodiments of the present invention facilitate the design of standard cell transistor gate dimensions, the benefits of the optimization can be easily analyzed either numerically or by way of inspection of easy to read graphical plots. These and other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.